【Key words】 IP Core; system on chip; reuse; common descrambling algorithm;
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An efficient method of the implementation, verification and test about DVB common descrambling algorithm proposed, and especially it focuses on the reuse design of the IP Core. This IP Core can freely interconnect with multifarious bus architectures.
提出了DVB通用解扰算法高性能IP核设计、验证和测试的方法,着重描述了IP核的可重用设计,使本IP核与多种总线能互连。
参考来源 - DVB通用解扰算法的高性能IP核设计·2,447,543篇论文数据,部分数据来源于NoteExpress
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