内存在突发式(Burst)读取模式下一次可连续读取4组数据,其读取周期可以表示为X-Y-Y-Y。其中X表示读取第一组数据的时钟周期数,一般叫做Lead off time(通常时间比较长);Y表示后三组数据的读写时间周期。
最后,在研究EP - H31580 1553总线芯片的基本功能和读写时序的基础上,完成了1553总线模块的硬件设计。
At last, 1553 bus circuit design has been finished on the basis of studying the basic function and timing of 1553 chip EP-H31580.
但SDRAM的控制时序和机制较复杂,因此需要设计sdram控制器以提高其读写效率。
While its time sequence and access mechanisms are very complex, it is necessary to design SDRAM controller to improve the efficiency of accessing.
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