这些方法编码和解码字节的方法依赖于缓冲区的字节顺序设置。
The way these methods encode or decode the bytes is dependent on the ByteBuffer's current byte-order setting.
在尽量减少时钟消耗的前提下，此解码器可以解码每个变换块中变换系数的熵编码码流，并将结果按照块扫描顺序并行输出。
While minimizing the use of clock cycles, it could decode the coded stream of transform coefficients in each block and output the decoded coefficients in zigzag scanning order.
介绍了一种以xcv300 FPGA为核心的视频接口设计。同时按照视频输入、解码存储、DAC转换输出视频流的流动顺序，给出了实现方法。
A video interface design based on XCV300FPGA is introduced. The implementations of video-in decoder and memory DAC video-out are discussed in detail.
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