XX节所描述的内部总线通过一组位于微处理器集成电路内的总线缓冲器与外部总线连接。
The internal processor bus described in Sec. XX is connected to the external processor bus by a set of bus buffers located on the microprocessor integrated circuit.
这一章的第一节对资本金的非预期损失缓冲器作用进行总结；
The first session of this chapter summarizes the unexpected loss buffer function of capital.
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