这样的体系结构可以跨越单一部门、多业务线(LOB)或商业组的成员。
Such architecture can span a single department, multiple lines of business (LOB), or members of a trading group.
本文提出了一种用我国首创的DY L集成线性“与或”门设计成的模拟延迟线。
AN artificial delay line which was designed by using the DYL integrated linear AND-OR gate created first in China were proposed.
该电路建立在一个简单的异或非逻辑门和延迟线的基础上，通过抽样调查异或非门的输出来检测电路的错误点，引入的多余面积很少。
The circuit is based on a simple XNOR logic gate and delay lines to sample the output of the XNOR gate, so very little area is introduced.
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