除此之外，既不减少错误覆盖率也不增加控制讯号，因此如我们所知，这是第一个以矽制程展示峰值功率降低的研究。
Besides, there is neither fault coverage degradation nor extra control signal. So far as we know, this is the first work to demonstrate the capture power reduction on silicon.
薄膜先以微影及蚀刻制程制作出金属线路，线路之间则填入二氧化矽。
The lithographic and etching process for a membrane creates a mesh of metal wires with silicon dioxide filling the space between them.
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