随着芯片面积的增加及电路复杂性的增强，芯片的成品率逐渐下降，为了保证合理的成品率，人们将容错技术结合入了集成电路。

An increase in chip area and circuit complexity leads to a reduction in the yield of chip production. In order to get a fair yield, the fault tolerant technique is introduced into the IC design.

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这也有不利的一面，更小的元件造成更高的复杂性并且需要散热方法避免其烧毁周围的电路。

There is a downside to this in that smaller components create more complexity and require some way of dissipating heat before it destroys the surrounding circuitry.

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主要障碍仍然反映我们的分子动力学参数非常简单化的理解，以及监管这些信号通路电路的复杂性。

Major hurdles still reflect our very simplistic understanding of both the kinetic parameters of the molecules involved as well as the complexity of the regulatory circuits of these signaling pathways.

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