该分频器采用源极耦合场效应管逻辑电路，基本结构与T触发器相同。
The divider is designed in the Source Coupled Logic, with the structure being similar to the t filp flop.
为了适应高速度的要求，所有电路全都采用源极耦合场效应管逻辑来实现。
In order to meet with the requirements of high-speed, the source coupled FET logic (SCFL) is applied in all of the circuits.
电路采用源极耦合场效应管逻辑（SCFL），与静态CMOS逻辑相比具有更高的速度。
SCFL circuits are used because of the higher speed compared to static CMOS.
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