堆栈结构也做了分析和优化，采用了两级流水线堆栈结构。
We also improve the stack architecture and use two-stage pipeline stack.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
本设计为兼顾模数转换器的速度和精度，采用数字校正技术，以每级1.5 位的9 级流水线结构实现。
The converter has a good tradeoff between conversion speed and conversion precision. It is a 1.5-bit per stage with 9 stage and digital correction technique.
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