速度优化通过流水线设计、寄存器配平或关键路径实现。
The work speed is optimized through the pipelining design, register matching or key path.
对于流水线型的超大规模微处理器，通常采用多端口的寄存器堆暂存中间数据，这些读写操作势必增加寄存器堆的芯片面积和功耗。
A multi-ported register file is often required by the superscalar microprocessor to handle multiple simultaneous loads and stores, which cause large increase in area and power consumption.
一种图形处理单元流水线，通过传送来自第一模块的围篱指令至寻址同步寄存器对而执行同步。
A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair.
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