通过使用第二代硅晶体和NiSi低电阻材料，Intel65纳米制程的栅长（Gate Length）和栅电容（GateCapacitance）都大幅度缩小，让漏电情况得到更好地控制（据称最多可以减少一千倍），从而大大减少能源损耗并增加电...
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Besides, when the gate length is fixed, with the ratio of the“control gate”length to the“screen gate”length increasing, the minimum surface potential has been decreasing.
此外,靠近漏端的金属的屏蔽作用增强,短沟道效应得到较大的改善;固定栅长下,控制栅和屏蔽栅的比例增大,最小表面势值减小。
参考来源 - 纳米SOI MOSFET的结构设计和性能分析·2,447,543篇论文数据，部分数据来源于NoteExpress
结果表明，随着栅长减小、栅间隙长度增加和沟道深度减小，传输栅电荷容量约从6。
It is shown that, as the gate length decreases, the gap width between the gates increases and the depth of the channel becomes shorter, the transmitted charge handling capacity will drop from 6.
在这种方法下，由于各种因素的影响，双栅器件的栅长、硅岛厚度呈现出不同的缩减限制。
Under this way, the gate length and thickness of Si island of DG device show many different scaling limits for various elements.
在该T型栅工艺中栅长和栅帽的尺寸分别进行控制，实现了较好的工艺可控性和较高的工艺成品率。
The gate length and the dimension of the gate head can be controlled in the T-shaped gate processing, and good process controllability and high yield can be achieved.
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