当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
重点锁定时钟是一个免费的时钟应用程序，而显示设备的关键锁定时。
Key lock Clock is a free Clock application that is shown while the device's key lock is on.
为了测试这个，做一个外部相位锁定的双时钟源，带有两个时钟有意调节相位关系的节点。
To test for this scenario, rig up an external phase-locked dual-clock source with a knob that intentionally adjusts the phase relationship of the two clocks.
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