中国信息产业网 - 一种基于FPGA的时钟数据恢复电路的设计实现 关键词： 时钟数据恢复；过采样；输入延时单元；现场可编程逻辑阵列 [gap=784]Keywords: clock data recovery; over-sample; IDELAY; FPGA
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...子质量E周刊 关键词： 时钟数据恢复；过采样；输入延时单元；现场可编程逻辑阵列 [gap=494]Key words: clock and data recovery;oversampling;input delay unit;field programmable logic arrays ..
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可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
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