说明：在fpga上是现奇数分频。可以更好的理解的FPGA开发的时序问题。

In the FPGA is the odd frequency. The development of FPGA timing problems can be better understood.

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设计人员通常在时序分析上花大量的时间和精力，因为一个微小的时序问题能导致整个设计的逻辑功能的错误。

Designers have to spend most of time and energy on timing analysis, because a slight mismatch would lead whole failure of entire logic function.

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针对DSP时序解决显示乱码问题。

DSP timing solution for the problem showed garbled.

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