... implementation-dependent instruction(依赖于处理器具体实现的指令) unimplemented instruction(未完成指令) invalid instruction(无效指令) ...
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如果数据或指令没有出现在高速缓存中，或者如果高速缓存线路无效的时候，CPU通过从主存储器中读数据来更新它的高速缓存。
If the data or instruction is not present in the cache, or if the cache line is invalidated, the CPU updates its cache by reading the data from the main memory.
在读操作中，如果发出了这个指令，那么两个时钟周期后，读出数据无效，数据总线进入高阻状态。
During a READ operation, When this command is issued, data outputs are disabled and become high impedance after two clock delay.
当一个缓存行中包含有有效的缓存数据或指令时这个缓存行就是有效的，反之是无效的。
A cache line is said to be valid when it contains cached data or instructions, and invalid when it does not.
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