提出了一种基于改进直接数字频率合成(DDS)技术的现场可编程门阵列(FPGA)数字调制器设计与实现方法。
In this paper a method of designing and implementing Field Programmable Gate Array (FPGA) digital modulator based on the improved Direct digital Synthesizer (DDS) technology is presented.
在FLL功能数字频率锁定环(FLL)的硬件，与数字调制器，稳定会计频率可编程多的观赏晶体频率。
The FLL features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
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