Integrally, the RISC CPU has BIU(Bus Interfacing Unit),IDU(Instruction Decoding Unit)-. ALU(Arithmatic&logic Unit),MMU(Memory Management Unit) etc.
从整体方面来说，整个微处理器大致分为BIU(总线接口单元)、IDU(指令译码单元)、ALU(算术逻辑单元)、MMU(存储管理单元)等等。
参考来源 - 64位RISC CPU在FPGA上的实现和验证And the decoder is composed by the pre-decoder, direct decoder and the micro-program ROM which controlled by instruction state machine.
指令译码器采用预译码技术,硬布线译码结合指令状态机控制的微码ROM的协同译码结构。
参考来源 - 一种16位数字信号处理器内核的研究与设计·2,447,543篇论文数据，部分数据来源于NoteExpress
当微处理器对该指令译码是，的操作序列来执行。
Each instruction may require a different sequence of operations to execute the instruction.
尽管图中没有显示，但指令译码器还有下列功能的控制线。
Although they are not shown in this diagram, there would be control lines from the instruction decoder.
按照指令译码的结果，这些指令的执行不会用到系统总线。
As with instruction decoding, the execution of these instructions does not make use of the system buses.
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