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这样，即使采用全扫描设计，也仅需较小的芯片面积。
Thus, only a very small extra chip area is required even if full scan design is used.
本文提出了扫描设计中存储元件在扫描链中的最优排序方法。
An optimal sequencing of the storage elements in the single scan chain design for - testability is presented in the paper.
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。
This paper presents a high speed test generation method specifically for upper large scale combination circuit (ULSCC) and full scan designed circuit.
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