异或门 （英语：Exclusive-OR gate，简称XOR gate，又称EOR gate、ExOR gate）是数字逻辑中实现逻辑异或的逻辑门。有多个输入端、一个输出端，多输入异或门可由两输入异或门构成。若两个输入的电平相异，则输出为高电平1；若两个输入的电平相同，则输出为低电平0。即如果两个输入不同，则异或门输出高电平1。
仿效卡诺图设计了以异或门为基本电路的电路设计用图—异或图。
The XOR map is presented that is a graphic for design base on exclusive-OR gate circuits and is follow the example of the Karnaugh map.
改进异或门拓扑结构实现的二倍频器，结构简单、实用，降低了电路复杂度。
The clock signal is obtained by using a frequency doubler which USES a modified XOR topology, so that the complexity of the system is reduced.
对于输出脉冲波形而言，LOA MZI异或门性能优于SOA MZI异或门。
LOA-MZI has better performance in output pulse shape than SOA-MZI.
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