该文设计出一种适用于硬件实现的单窗口全通道并行编码结构，目前已通过FPGA验证。

In this paper, a hardware-oriented, full pass-parallel coding architecture is presented, based on only one scanning window. This architecture is verified on FPGA.

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通过研究EBCOT编码原理和通道并行算法的编码过程，提出了双上下文窗口位并行的EBCOT系数位建模方法，详细说明了使用该算法的系数位建模系统的硬件结构。

After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.

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研究了现有的位平面编码VLSI结构，设计了一种条带列与编码通道全并行的VLSI结构，解决了内部存储资源占用率高的问题。

According to the research on the existing VLSI architecture of the bit-plane coding, a new VLSI architecture is proposed in which stripe-column and coding are both implemented in parallel.

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