通过对数据接收电路CPLD内部参数的调整，可以实现对各种数字接口器件的配置，从而使得电路控制更加简单、灵活与可靠。
By adjusting parameters in CPLD of data receiving circuits, we can implement configuration of all kinds of digital interface devices, which makes the circuit control simpler, neater and more reliable.
文章对数字集成电路设计中的时序分析作了一个概要的介绍。
The timing analysis in the design of digital integrated circuits is described.
我们在最后的结论中提出了一个构想：构造少数几个对数域电路基元，再利用电路基元来简化用于连续小波变换实现的模拟电路设计。
In the final conclusion, we propose a ideal: by constructing few cells of log-domain circuits we use these cells to simplify the design of analog circuits for implementation of the CWT.
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