随着半导体工艺的进步，芯片集成度和运算速度的提高，互连寄生效应的影响也日益明显。

The influence of parasitic interconnect capacitance is much in evidence with the progress of the semiconductor techniques and the increase of chip density and calculated speed.

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对互连寄生电容提取的研究背景进行了简要的介绍。

In this paper, the background of parasitic capacitance extraction of interconnects are briefly introduced.

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在3d VL SI互连寄生电容的边界元素法计算中，多孔平面的边界元划分是十分困难的问题。

In the computations of 3d VLSI parasitic interconnect capacitance, it is very difficult to partition the boundary elements on a multi hole surface.

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