上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。
The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.
提出使用网表示可分配寄存器对象，通过对网的活跃性数据流分析，构造网的冲突图。
This paper presents Web as the object to be assigned to registers, constructs the interference graph of Webs by data flow analysis of Web liveness.
介绍了一种对定时器、计数器、数据寄存器的数据进行外部设定并显示的电路，并给出了相应的梯形图程序。
This paper introduces a circuit setting up and displaying the data of timer, counter and data register out of PLC. It gives the ladder-type Patterned program.
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