A debug model of embedded processors is founded with the state set of storage elements, and an in-depth analysis is given on the principles, inherent advantages and realization models of on-chip trace.
建立了基于存储元件状态集合的嵌入式处理器调试模型,对片上trace的工作机理、内在优势和实现模型进行了深入分析和讨论。
参考来源 - 嵌入式多核处理器在线追踪调试与错误检测关键技术研究·2,447,543篇论文数据，部分数据来源于NoteExpress
论述了虚拟仪器在存储元件测量中的应用；
The application of virtual instrument (VI) in memory component testing is described in this paper.
看作是一个存储单位的一个或多个存储元件。
本文提出了扫描设计中存储元件在扫描链中的最优排序方法。
An optimal sequencing of the storage elements in the single scan chain design for - testability is presented in the paper.
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