数字抽取滤波器是它的重要组成部分，通常采用多级结构来实现。
The digital decimation filter taking the important constituent in the Delta-Sigma Analog-to-Digital converter is realized by the multistage structure.
将可编程抽取、插值器与多级积分梳状滤波器（CIC）相配合，实现高效数字抽取和插值模块。
A programmable decimation and interpolation ratio module onnected with multistage cascade integrator comb (CIC) filter is designed to implement high efficient decimator and interpolator.
研究了高倍抽取的数字下变频设计，重点分析了基于级联积分梳状滤波器、级联补偿滤波器、级联根升余弦滤波器的多级抽样频率算法。
In this paper, the high decimation ratio of digital down converter is studied and the multi-stage decimation algorithm is especially analyzed based on CIC filter, CFIR filter and RRC filter.
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