提出了一种高速低功耗脉冲寄存器的设计方法，并将其应用在高速DSP地址生成单元的设计中。
This paper proposes a high speed and low power pulse latch design, and integrates it to high speed DSP address generator.
RAM地址生成单元，被配置为基于偏移选择信号而生成与该ROM读取地址对应的RAM读取地址；
The RAM address generating unit generates a read RAM address corresponding to the read ROM address based on the offset select signals.
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