访问内部统一二级处理器缓存的后端总线接口逻辑。

Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.

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EAI蕴含的基本假定是，集成在后端进行，使用不是星形结构（hub and spoke），就是总线架构。

The fundamental premise behind EAI is that the integration is performed on the back end, using either a hub and spoke or bus architecture.

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本论文所设汁的PCI总线控制器以LCD显示器为后端设备，完成PCI主设备与LCD显示器之间的通信。

The designed PCI controller in this-subject, using a LCD display as backend device, performs the communication between PCI master and LCD display.

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