该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
在应用方案中，讨论了利用北斗卫星定位系统、全球卫星定位系统(GPS)和原子时钟构建最高级时钟的冗余配置方案。
In the proposed schemes, the redundant configuration of grandmaster clock using Beidou navigation satellite system, GPS (Global Positioning system) and atomic clock is discussed.
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