另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。
Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.
本文提出了采用模拟多路开关的模拟内建自测试电路abist的一种新结构。
This paper presents a new structure of analog Built - in Self - Test circuit (ABIST) consisting of analog multiplexers.
文中详细分析了嵌入式存储器内建自测试的实现原理，并给出了存储器内建自测试的一种典型实现。
The principle of memory built-in self-test is analyzed in detail and a typical implementation of MBIST is given in the paper.
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