动画帧所有网格顶点包含着顶点的位置(可能包括法线)其全部储存在内存中。

Vertex positions (may include normals also) for all the vertices in the mesh for all the animation frames are stored in memory.

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全部电路由硬件描述语言实现，可以集成在一片CPLD或FPGA芯片内部，用于数字通信系统接收端的帧同步和定时。

All circuits are designed by HDL and can be intergrated in one CPLD or FPGA chip, used in the frame synchronization and timing of digital communications receiver.

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二层的帧必须等到所有比特全部接收通过CRC(环冗余校验)验后才能被处理。

Layer2 frame cannot be processed by a receiver until all bits have been received by the receiver and a cyclic redundancy check (CRC) has been performed.

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