这样，即使采用全扫描设计，也仅需较小的芯片面积。
Thus, only a very small extra chip area is required even if full scan design is used.
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。
This paper presents a high speed test generation method specifically for upper large scale combination circuit (ULSCC) and full scan designed circuit.
全扫描设计中的数据包括测试激励数据以及测试响应所对应的期待响应值。
The design of full-scan data includes test data and the corresponding test response in general, which are stored in the memory of Automatic Test Equipment (ATE).
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