Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
参考来源 - 面向电机控制数字信号处理器设计和测试研究·2,447,543篇论文数据，部分数据来源于NoteExpress
评估全扫描定量结果。
这样，即使采用全扫描设计，也仅需较小的芯片面积。
Thus, only a very small extra chip area is required even if full scan design is used.
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。
This paper presents a high speed test generation method specifically for upper large scale combination circuit (ULSCC) and full scan designed circuit.
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