首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。

Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.

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本文结合纳米级工艺下互连线特性，对互连串扰噪声与延时的相关问题进入了深入的研究探讨。

This paper makes a deep research and discussion for crosstalk noise and interconnect delay combined the interconnect lines characteristic in nanometer process.

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