在串行呈现模式中，从所有后端系统检索所需数据的总体延迟为各个延迟时间的总和。
In serial rendering mode, the overall latency for retrieving the required data from all the backend systems would have to be calculated as the sum of the individual latency times.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
为了提高单个量子阱半导体光放大器的可调光子延迟，我们进一步探讨了多个光放大器的串行级联。
To enhance the tunable photonic delay of a single QW SOA, we explore a serial cascade of multiple amplifiers.
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