VHDL language VHDL语言
the VHDL language VHDL语言
VHDL language reference manual VHDL语言参考手册
VHDL language design VHDL语言设计
VHDL language portal 说明vhdl
vhdl language description vhdl语言描述
application of vhdl language vhdl设计方法应用
VHDL Hardware Description Language VHDL硬件描述语言
The hardware description language VHDL 硬件描述语言VHDL
The serial communication interface chip design was realized by application of schematic diagram and VHDL language.
采用自顶向下的设计方法，用原理图和VHDL语言这两种输入对串行通信接口芯片进行设计。
Having analyzed the difference of the two languages, this paper provides a method of translating C language into VHDL language, and the method is implemented.
文章通过分析两种语言的区别，提出并实现了适于表达C语言描述内容的VHDL结构形式，并对几种C语言结构提出合理的转换方案。
The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.
VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。
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