With the complex programmable logic devices (CPLD) a wide range of applications to the development of EDA tools as a means of the use of VHDL.
随着复杂可编程逻辑器件（CPLD）的广泛应用，以EDA工具作为开发手段，运用VHDL语言。
Use VHDL to write a dynamic RAM reading and writing processes, including project documents can be directly used, several projects.
用VHDL写的一个动态ram读写程序，包括工程文件可直接便用，多次用项目中。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
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