bus-timing emulation 总线时序仿真
timing signal bus out 定时信号输出总线
Bus Timing 总线时序 ; 总线定时
TSBO Timing Signal Bus Out 定时信号输出总线
bus interface timing 总线接口时序
In this paper, an ASIC based on PCI Local Bus SpecificationV2.2 is designed, and its function, timing characteristic and design flow are also presented.
研究并设计了符合PCI规范V2.2的接口芯片，着重阐述了它的功能特点、时序特征及其大致设计流程。
The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing.
根据PCI总线操作时序，提出了从设备接口控制器的有限状态机模型。
Programmable hardware timing was used in design of microsecond synchronizer based on ISA bus, after pulse generated by oscillator was divided frequency, it was sent to 8254 to count.
基于IS A总线的微秒级同步器采用可编程硬件定时，由晶振发出脉冲经分频后送入8254计数。
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