With the help of IC back-end tools, this generator could implement the checking and verifying of the generated test structures layout files.

生成器配合集成电路后端设计开发环境，可以对所生成的测试结构版图文件进行检查与验证。

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The operation of checking and verifying work shows that this generator can generate the test structures layout files automatically, efficiently and accurately.

实际操作过程中的检查与验证表明，此生成器可以快速有效地自动生成正确的测试结构版图文件。

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Organization of the test cases into a rigid hierarchical structure of nested folders makes it difficult to take the test cases out of those structures and reuse them.

将测试用例组织到一个僵硬的层级结构的文件夹结构中，将会使得从结构中取出它们变得十分困难，也不方便再使用。

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The test chip will enable the correlation of the simulation models to the FinFET process and contains test structures, standard cells, a PLL and embedded SRAMs. The memory instances include high-density SRAMs designed to operate at very low voltages and high-speed SRAMs to validate the process performance.

ENGADGET: Samsung reveals its first 14nm FinFET test chip, should offer substantial power improvements in future silicon