The systolic VLSI was designed to perform the new algorithm, followed by complexity analysis.

此外，为该算法设计出脉动阵列VLSI结构，并和现有结构进行了对比分析。

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To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.

同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。

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This structure divides wavefront control calculation into recursive algorithm and convolution algorithm, and maps them to respectively systolic array by using canonical mapping method.

该结构将波前控制算法分为递归运算和卷积运算两部分后，采用规范映射方法将其分别映射到脉动阵列，再将两个阵列链接以实现单路的波前控制运算。

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