On the basis of the architecture, the thesis describes the whole design in Verilog HDL at the full synthesizable RTL level with synchronous design technology.
在完成硬件结构设计的基础上,使用Verilog硬件描述语言对整个设计进行了完全可综合的RTL级描述,采用同步设计,提高了可靠性。
参考来源 - 二维离散小波变换的FPGA实现·2,447,543篇论文数据，部分数据来源于NoteExpress
The asynchronous design and synchronous design are the two basic methods in implementing the digit system.
异步设计与同步设计是两种基本的数字电路系统实现方法。
The asynchronous design and synchronous design are the two basic methods in implementing the digital system.
异步设计与同步设计是两种基本的数字电路系统实现方法。
The method of synchronous design feature and machining feature modeling based on local feature recognition is presented in Chapter 3.
第三章介绍基于局部特征识别的设计特征和加工特征同步建模方法。
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