Asystemperformancemodel of high performance microprocessor is implemented, which is based onsuperscalar pipelinetechnology with the instruction set of i960KA.
The Brahma15 is a 21, 000 DMIP Quad-core ARMv7-A instruction set compatible multiprocessor. 32KB instruction and 32KB data caches per processor are backed by a shared 2MB L2 cache and feed the multi-issue, out-of-order superscalar 15-stage plus write back pipeline of the Brahma15.