Update Subcircuits Symbols 更新子电路符号
Subcircuits and Hierarchy 子电路和层次设计
Subcircuits module 子电路模块
frequent subcircuits 频繁子电路
A general fault analysis model is obtained for subcircuits.
给出了子电路的一般故障分析模型。
The algorithm divides a complex dynamic circuit into some linear subcircuits and link branches (linear and nonlinear).
把复杂动态电路分割成若干个线性子电路和一组联络支路（线性和非线性）。
Based on the analysis of the theory of CPPLL and application requirements in the DSP, the structure and the performance specifications of the PLL are defined, and then the subcircuits are designed.
文章在深入分析电荷泵锁相环设计理论的基础上，根据DSP芯片对锁相环的具体应用要求，确定了锁相环的总体电路结构和各项性能参数。
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