These include pre- and post-increment/decrement ( i++, --foo ), add/sub/mult/div assign operators ( a+=3, b*=2, c/=2.2, d-=6.2 ).
其中包括前后加/减（i++、--foo）， 加减乘除赋值运算符（a+=3、b*=2、c/=2.2、d-=6.2）。
That is needed: sub-Saharan Africa spends much less than India on agricultural R&D.
这恰是非洲需要的：撒拉哈以南非洲在农业研发上的开支甚至远远低于印度。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
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