At last, the layout of the sub-ADC has been designed. The area is 115μm×60μm.
子ADC版图面积为115μm×60μm。
参考来源 - 基于流水线模数转换器的子ADC的研究与设计·2,447,543篇论文数据，部分数据来源于NoteExpress
A differential pair dynamic comparator which has no DC power dissipation is used in SUB-ADC.
每级子模块中采用了没有直流功耗的差分对动态比较器，具有更好的综合性能。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
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