... state machine description language 状态机描述语言 state description scheme 状态描述模式 state description compiler 状态描述编译程序 ...
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A design method by usage of finite state machine and VHDL hardware description language to develop the program is adopted, then it is simulated and downloaded on the EDA software platform.
采用有限状态机设计方法,使用VHDL硬件描述语言编程,并在EDA工具软件平台上进行了仿真和下载。
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