Multi Stacked-Die Packaging 多晶片堆叠封装
Stacked-Die Packaging 晶片堆叠封装
Stacked-Die Packages 堆栈裸片封装
stacked die chip 叠层芯片
stacked die packaging 叠层芯片封装
stacked-die chip scale package 叠层芯片尺寸封装
Stacked-Die Low-Profile Fine-Pitch BGA 低外形细节距球栅阵列堆叠芯片
The finite element analysis (FET) software ANSYS have been used to simulate the temperature and stress distribution in stacked die package under power load.
应用有限元分析软件ANSYS，模拟功率载荷下叠层芯片封装中各层的温度和应力分布。
This is also preformed on covered surfaces a stacked assembly : substrate - pre - form - die.
在叠层的组装工艺中，比如基板- 焊片- 芯片，即使有部分表面被盖住了，这种气氛同样有效。
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