The test architecture reusing data bus as TAM can reduce the silicon area cost for DFT greatly.
复用数据总线作为测试传输机构的测试结构可以大大减小可测性设计的面积开销。
It also meant that ATI spent a lot of silicon area implementing things that would never be used.
这也意味着AT I公司花费了大量的芯片面积实施的事情永远不会被使用。
This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance.
这种先进的工艺技术达到最低可能在每硅阻力区,在出色性能。
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