The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The chip is a crosspoint array with 32 outputs, each of which can be connected to any one of 32 inputs. The chip is programmed in serial mode.
所设计的芯片是32个输入32个输出的交叉点开关阵列，每一个输出都能连接任何一路输入，采用串行数字控制方式。
It first detects impulse noises in an image in a serial mode, and the threshold, which is used to estimate noise pixel, can be modified adaptively.
该方法首先采用串行方式，对含有脉冲噪声的图像进行逐点检测，其中判断噪声点的阈值可自适应地调整。
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