This paper presents a high speed PCM demodulation circuit through which the serial parallel converter plays a role of demodulating and the hardware realizes frame synchronization.
为了从接收到的PCM码中还原出原始信号，阐述了一种由硬件实现帧同步，由串并转换器完成PCM码解调器的高速PCM码解调器电路。
It USES FPGA as its main control chip. The FPGA comprises a spike generator, a serial-to-parallel converter and some multiplexers.
采用FPGA作为主控芯片，在FPGA内部设计了刺激脉冲发生器，多路选择器和串并转换器。
In the design and application of ultra-high-speed parallel-to-serial converter, a new method is proposed, which is called duplex constant-current-source structure(DCS).
在超高速并串转换接口电路设计应用中，提出了一种新的双路恒流结构方式。
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