Sequential logic synthesis is an important part of RTL synthesis system design.

时序逻辑综合是RTL综合系统设计中的一个重要部分。

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Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.

此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。

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